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Z87233
CMOS Z8(R) MCU Consumer Controller Processor
Product Specification
PS022701-0104
ZiLOG Worldwide Headquarters * 532 Race Street * San Jose, CA 95126-3432 Telephone: 408.558.8500 * Fax: 408.558.8300 * www.ZiLOG.com
(c)2004 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval of ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
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Table of Contents
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Expanded Register File, Bank 0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Expanded Register File, Bank Fh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extended Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 32 32 42 47 47 48 52 55 60 60
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Precharacterization Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Document Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Document Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Customer Feedback Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z87233 Product Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Customer Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Return Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Problem Description or Suggestion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 64 64 64 64 65
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List of Figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 28-Pin DIP/SOIC Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Port 0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Port 2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Port 3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Port 3 Configuration--PCON Register Detail . . . . . . . . . . . . . . . . . 10 Program Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Register Pointer--Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Expanded Register File Architecture . . . . . . . . . . . . . . . . . . . . . . . . 16 Counter/Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Oscillator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Stop-Mode Recovery Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Resets and Watch-Dog Timer Example . . . . . . . . . . . . . . . . . . . . . 30 Typical Low-Voltage Protection vs. Temperature . . . . . . . . . . . . . . 31 Additional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Test Load Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 28-Pin DIP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 28-Pin SOIC Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
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List of Tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Family Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 28-Pin DIP/SOIC Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Port 3 Pin Assignments 8 Register Pointer Register--RP FDh/R253 Bank 0h: READ/WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Interrupt Types, Sources, and Vectors . . . . . . . . . . . . . . . . . . . . . . 18 IRQ Register* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Port Configuration Register--PCON 00h/R0 Bank Fh: WRITE ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Stop-Mode Recovery Register 1--SMR1 0Bh/R11 Bank Fh: WRITE ONLY, except Bit D7, which is READ ONLY . . . . . . . . . . . 23 Stop-Mode Recovery Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Stop-Mode Recovery Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Stop-Mode Recovery Register 2--SMR2 0Dh/R13 Bank Fh: WRITE ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Watch-Dog Timer Mode Register--WDTMR 0Fh/R15: WRITE ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 WDT Time Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Maximum (VLV) Conditions: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Expanded Register File Registers--Reset States . . . . . . . . . . . . . . 32 Timer Mode Register--TMR F1h/R241 Bank 0h: READ/WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Counter/Timer 1 Register--T1 F2h/R242 Bank 0h: READ/WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Prescaler 1 Register--PRE1 F3h/R243 Bank 0h: WRITE ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Counter/Timer 0 Register--T0 F4h/R244 Bank 0h: READ/WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Prescaler 0 Register--PRE0 F5h/R245 Bank 0h: WRITE ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Port 2 Mode Register--P2M F6h/R246 Bank 0h: WRITE ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Port 3 Mode Register--P3M F7h/R247 Bank 0h: WRITE ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Ports 0 and 1 Mode Register--P01M F8h/R248 Bank 0h:
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Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42.
WRITE ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Priority Register--IPR F9h/R249 Bank 0h: WRITE ONLY Interrupt Request Register--IRQ FAh/R250 Bank 0h: READ/WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Mask Register--IMR FBh/R251 Bank 0h: READ/WRITE . Flags Register--FLAGS FCh/R252 Bank 0h: READ/WRITE . . . . . Register Pointer--RP FDh/R253 Bank 0h: READ/WRITE . . . . . . . General Purpose--GPR FEh/R254 Bank 0h: READ/WRITE . . . . . Stack Pointer Low--SPL FFh/R255 Bank 0h: READ/WRITE . . . . . Expanded Register File Registers--Reset States . . . . . . . . . . . . . . Port Configuration Register--PCON 00h/R0 Bank Fh: WRITE ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop-Mode Recovery Register--SMR 0Bh/R11 Bank Fh: READ/WRITE Stop-Mode Recovery Register 2--SMR2 0Dh/R13 Bank Fh: WRITE ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watch-Dog Timer Mode Register--WDTMR 0Fh/R15 Bank Fh: WRITE ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Electrical Characteristics at Standard Temperature . . . . . . . . . DC Electrical Characteristics at Extended Temperature . . . . . . . . . Additional Timing at Standard Temperature . . . . . . . . . . . . . . . . . . Additional Timing at Extended Temperature . . . . . . . . . . . . . . . . . . Capacitance* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36 37 38 39 40 41 41 42 42 43 44 45 46 47 48 52 56 58 60 62
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Architectural Overview
ZiLOG's large Z8(R) family of 8-bit microcontrollers now includes the Z87233 product line, featuring an enhanced wake-up circuitry, programmable Watch-Dog Timers (WDT), and low-noise/EMI options. These enhancements to the Z8 offers a more efficient, cost-effective design and provides the user with increased design flexibility over the standard Z8 microcontroller core. The low-power-consumption CMOS microcontroller offers fast execution, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, and easy hardware/software system expansion. The Z87233 subfamily features an Expanded Register File (ERF) to allow access to register-mapped peripheral and I/O circuits. Four basic address spaces are available to support this wide range of configurations: Program Memory, Register File, and ERF. The Register File is composed of 237 bytes of general-purpose registers, three I/O port registers, 15 control and status registers. The ERF consists of four control registers. For applications demanding powerful I/O capabilities, the Z87233 offers 24 pins dedicated to input and output. These lines are configurable under software control. The Z87233 family operates at 4MHz with a voltage range of 3.0 to 5.5VDC. To unburden the system from coping with real-time tasks such as counting/timing, the Z8 offers two on-chip counter/timers with a large number of user-selectable modes. Note: All signals with an overline are active Low. For example, B/W, for which WORD is active Low, and B/W, for which BYTE is active Low. Power connections follow these conventional descriptions:
Connection Power Ground Circuit VCC GND Device VDD VSS
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Features
Table 1. Family Features Device Z87233 ROM (KB) RAM* (Bytes) Speed (MHz--Standard and Extended Temperature) 8 236 4
Note: *General-Purpose.
* * * * * * * * * * * *
28-Pin DIP and 28-Pin SOIC 3.0- to 5.5-Volt Operating Range Operating Temperature Ranges: Standard: 0C to 70C Extended: -40C to +105C Expanded Register File (ERF) 24 Input/Output Lines Vectored, Prioritized Interrupts with Programmable Polarity Two Analog Comparators Two Programmable 8-Bit Counter/Timers, each with two 6-Bit Programmable Prescalers VBO/Power-On Reset (POR) Clock-Free Watch-Dog Timer (WDT) Reset On-Chip Oscillator that accepts a Crystal, Ceramic Resonator, LC, RC, or External Clock RAM and ROM Protect
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Functional Block Diagram
Output Input VCC GND
XTAL
Port 3
Machine Timing & Inst. Control ALU RESET WDT, POR
Counter/ Timers (2)
Interrupt Control
FLAG
Prg. Memory 8K
Two Analog Comparators
Register Pointer Register File Program Counter
Port 2 4 I/O (Bit Programmable)
Port 0 4
Address or I/O (Nibble Programmable)
Figure 1. Functional Block Diagram
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Pin Description
P25 P26 P27 P04 P05 P06 P07 VDD XTAL2 XTAL1 P31 P32 P33 P34
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
P24 P23 P22 P21 P20 P03 VSS P02 P01 P00 P30 P36 P37 P35
Figure 2.28-Pin DIP/SOIC Pin Configuration
Table 2. 28-Pin DIP/SOIC Pin Configuration Pin # 1-3 4-7 8 9 10 11-13 14-15 16 17 18 19-21 22 23 24-28 Symbol P25-27 P04-07 VDD XTAL2 XTAL1 P31-33 P34-35 P37 P36 P30 P00-02 VSS P03 P20-24 Function Port 2, Pins 5,6,7 Port 0, Pins 4-7 Power Supply Crystal Oscillator Crystal Oscillator Port 3, Pins 1,2,3 Port 3, Pins 4,5 Port 3, Pin 7 Port 3, Pin 6 Port 3, Pin 0 Port 0, Pins 0,1,2 Ground Port 0, Pin 3 Port 2, Pins 0,1,2,3,4 Input/Output Input/Output Output Input Fixed Input Fixed Output Fixed Output Fixed Output Fixed Input Input/Output Direction Input/Output Input/Output
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Pin Functions
The following pages describe the function of each available Z87233 family pin.
XIN Crystal Input. This pin connects a parallel-resonant crystal, ceramic resonator,
LC, or RC network, or an external single-phase clock to the on-chip oscillator input.
XOUT Crystal Output. This pin connects a parallel-resonant crystal, ceramic reso-
nant, LC, or RC network to the on-chip oscillator output.
Port 0 (P00-P07). Port 0 is an 8-bit, bidirectional, CMOS-compatible port. These
eight I/O lines are configured under software control as a nibble I/O port (P03-P00 input/output and P07-P04 input/output), or as an address port for interfacing external memory. The input buffers are Schmitt-triggered and nibble-programmed as outputs and can be globally programmed as either push-pull or open-drain. Low-EMI output buffers are globally programmed by the software.
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4 Port 0 (I/O)
Z8
4
Open-Drain OE
PAD
Out 1.5 In 2.3 Hysteresis VCC @ 5.0V
Auto Latch (Mask Option) R ~ 500 k ~
Figure 3. Port 0 Configuration
Port 2 (P27-P20). Port 2 is an 8-bit, bidirectional, CMOS-compatible I/O port.
These eight I/O lines are configured under software control as an input or output, independently. Port 2 is always available for I/O operation. The input buffers are Schmitt-triggered. Bits programmed as outputs may be globally programmed as either push-pull or open-drain. Low-EMI output buffers are globally programmed by the software. See Figure 5.
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Z8
Port 2 (I/O)
Open Drain Open PAD
Out 1.5 In 2.3 Hysteresis VCC @ 5.0V
Auto Latch (Mask Option) R ~ 500 k
Figure 4.Port 2 Configuration Port 3 (P37-P30). Port 3 is an 8-bit, CMOS-compatible port, with four fixed inputs
(P33-P30) and four fixed outputs (P34-P37). Port 3 is configured under software control for Input/Output, Counter/Timers and interrupt. Port 3, bit 0 input is Schmitt-triggered, and pins P31, P32, and P33 are standard CMOS inputs (no autolatches). Pins P34, P35, P36, P37 are push-pull output lines. Low-EMI output buffers are globally programmed by the software. Two onboard comparators process analog signals on P31 and P32 with reference to the voltage on P33. The analog function is enabled by programming Port 3
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Mode Register (P3M bit 1). For interrupt functions, Port 3, bit 0 and pin 3 are falling-edge interrupt inputs. P31 and P32 are programmable as rising, falling, or both edge-triggered interrupts (IRQ register bits 6 and 7). P33 is the comparator reference voltage input when in Analog mode. Access to Counter/Timer 1 is made through P31 (TIN) and P36 (TOUT). Port 3 also provides the following control functions: four external interrupt request signals (IRQ3-IRQ0) and timer input and output signals (TIN and TOUT).
Table 3. Port 3 Pin Assignments Control Timer
Pin P30 P31 P32 P33 P34 P35 P36 P37
I/O IN IN IN IN OUT OUT OUT OUT
Analog
Interrupt IRQ3
TIN
AN1 AN2 REF AN1-OUT
IRQ2 IRQ0 IRQ1
TOUT AN2-OUT
Comparator Inputs and Outputs. Port 3, pins P31 and P32 each feature a comparator front end. The comparator reference voltage, pin P33, is common to both comparators. In ANALOG mode, the P31 and P32 are the positive inputs to the comparators, and P33 is the reference voltage supplied to both comparators. In DIGITAL mode, pin P33 is used as a P33 register input or IRQ1 source. P34 and P37 can provide the comparator output directly by software-programming the PCON register bit D0 to 1 (see Figure 5).
Note: The user must add a two-NOP delay after setting the P3M bit D1 to 1 before the comparator output is valid. IRQ0, IRQ1, and IRQ2 must be cleared in the IRQ register when the comparator is enabled or disabled.
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Z8
Port 3 (I/O or Control)
Auto Latch (Programmable Option)
P30 R247 = P3M D1 0 = Digital 1 = Analog
P30 Data Latch IRQ3
P31 (AN1) + -
DIG. IRQ2, TIN, P31 Data Latch ANL.
P32 (AN2) + P33 (REF) -
IRQ0, P32 Data Latch
IRQ1, P33 Data Latch From Stop-Mode Recovery Source
Figure 5. Port 3 Configuration
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P34 OUT P34 P31 REF (P33) + P37 + PCON D0 0 P34, P37 Standard Output 1 P34, P37 Comparator Output PAD PAD
P37 OUT P32 REF (P33)
Figure 6.Port 3 Configuration--PCON Register Detail Autolatch. The autolatch places valid CMOS levels on all CMOS inputs (except P33-P31) that are not externally driven. Whether this level is 0 or 1 cannot be determined. A valid CMOS level, rather than a floating node, reduces excessive supply current flow in the input buffer. Autolatches are available on Port 0, Port 1, Port 2, and P30. There are no auto latches on P31, P32, and P33.
Note: Deletion of all port autolatches is available as an option when the device is programmed. The AUTOLATCH DISABLE option is selected by the customer when the device is programmed.
Functional Description
The Z8 MCU incorporates the following functions that enhance the standard Z8(R) architecture and provide the user with increased design flexibility:
* * * * * * *
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Program Memory ROM Protect RAM Protect Working Register File Expanded Register File General-Purpose Registers Stack Pointer
Z87233 CMOS Z8" MCU Consumer Controller Processor
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* * * * * * * * * * * * * *
Counter/Timers Interrupts Clock Power-On Reset HALT and STOP Modes Port Configuration Register Comparator Stop-Mode Recovery Watch-Dog Timer Voltage Comparator (VLV)
RESET. The device is reset in one of the following conditions.
Power-On Reset Watch-Dog Timer Stop-Mode Recovery Source Low Voltage Recovery
Automatic Power-On Reset circuitry is built into the MCU eliminating the requirement for an external reset circuit to reset upon power-up.
Program Memory. The Program Memory addresses up to 8 KB of internal memory. The first 12 bytes of program memory are reserved for the interrupt vectors. These locations contain six 16-bit vectors that correspond to the six available interrupts. Address 12 to address 8191 consists of on-chip mask-programmed ROM.
The 8 KB program memory is mask programmable. A ROM protect feature prevents dumping of the ROM contents by inhibiting execution of LDC, LDCI, LDE, and LDEI instructions to program memory from any external program mode. ROM look-up tables can be used with this feature. The ROM Protect option is mask-programmable, to be selected by the customer when the ROM code is submitted.
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See Figure 7.
65537 8192 8191 Location of first Byte of Instruction Executed after RESET 12 11 10 9 8 Interrupt Vector (Lower Byte) 7 6 5 Interrupt Vector (Upper Byte) 4 3 2 1 0
Reserved On-Chip ROM
IRQ5 IRQ5 IRQ4 IRQ4 IRQ3 IRQ3 IRQ2 IRQ2 IRQ1 IRQ1 IRQ0 IRQ0
Figure 7.Program Memory Map ROM Protect. ROM PROTECT provides an additional security function. When the ROM PROTECT option bit is selected, and executing out of Internal Program Memory, instructions LDC, LDCI, LDE, and LDEI can read Internal Program Memory. RAM Protect. The upper portion of the RAM's address spaces 80h to EFh (exclud-
ing the control registers) can be protected from writing. The RAM Protect option bit can be selected when the device is programmed. After the mask option is selected, the user activates this feature from the internal ROM code to turn off/on the RAM Protect by loading either a 0 or a 1 into the IMR register, bit D6. A 1 in bit D6 enables the RAM Protect option.
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Working Register File. The Z8 standard register file (Bank 0) contains 3 I/O port registers, 237 general-purpose registers, and 15 control and status registers. Expanded register file Bank Fh contains 4 system-configuration registers. The working registers are accessed directly or indirectly via an 8-bit address field. As a result, a short 4-bit register address can use the Register Pointer (Table 5 and Figure 9). In the 4-bit mode, the working register file is divided into 16 working register groups, each occupying 16 continuous locations. The Register Pointer addresses the starting location of the active working register group.
Throughout this document, Bank 0 is referred to as the Z8 Standard Register File.
Table 4. Register Pointer Register--RP FDh/R253 Bank 0h: READ/WRITE Bit R/W Reset D7 R/W 0 D6 R/W 0 D5 R/W 0 D4 R/W 0 D3 R/W 0 D2 R/W 0 D1 R/W 0 D0 R/W 0
Note: R = Read, W = Write, X = Indeterminate.
Bit Position D7-D4 D3-D0
Bit Field Working Registers ERF
R/W R/W R/W
Reset State Description 0 0 Working Register Group Pointer Expanded Register File
Expanded Register File (ERF). The Z8 register file is expanded to allow for addi-
tional system control registers, and for mapping of additional peripheral devices, along with the I/O ports, into the register address area. The Z8 register address space 0 through 255 is implemented as 16 groups of 16 registers per bank (Figures 8 and 9 ). There are 16 banks known as the Expanded Register File (ERF). Bits 7-4 of register RP select the Working Register Group. Bits 3-0 of register RP select the Expanded Register File Bank. Four system configuration registers reside in the Expanded Register File at Bank Fh--PCON, SMR, SMR2, and WDTMR. The remainder of the Expanded Register is not physically implemented, and is open for future expansion.
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r7 r6 r5 r4
r3 r2 r1 r0
R253 (Register Pointer)
This upper nibble of the register file address provided by the register pointer specifies the active working-register group.
FF F0 EF 80 7F 70 6F 60 5F 50 4F 40 3F 30 2F 20 1F 10 0F 00
Register Group Fh
R15 to R0
Specified Working Register Group
The lower nibble of the register file addresses provided by the instruction points to the specified register. R15 to R0 R15 to R4* R3 to R0*
Register Group 1 Register Group 0 I/O Ports
* Expanded Register File Bank 0 is selected in this figure by handling bits D3 to D0 as "0" in Register R253 (RP).
Figure 8.Register Pointer--Detail General-Purpose Registers (GPR). General-purpose registers are undefined after
the device is powered up. These registers keep the most recent value after any RESET, as long as the RESET occurs in the VCC voltage-specified operating range. General-purpose registers are not guaranteed to keep their most recent state from a Low-Voltage Protection (VLV) RESET if VCC drops below 1.8V.
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Note:
Register E0h-EFh is only accessed via working register and indirect addressing modes.
Stack Pointer. The internal register file is used for the stack. An 8-bit Stack Pointer
(SPL) is used for the internal stack that resides within the 236 general-purpose registers. Stack Pointer High (SPH) is used as a general-purpose register. Note: SPH and SPL are set to 00h after any RESET or Stop-Mode Recovery.
Counter/Timers. There are two 8-bit programmable counter/timers (T0-T1), each driven by its own 6-bit programmable prescaler. The T1 prescaler is driven by internal or external clock sources; however, the T0 prescaler is driven by the internal clock only (Figure 10).
The 6-bit prescalers can divide the input frequency of the clock source by any integer number from 1 to 64. Each prescaler drives its counter, which decrements the value (1 to 256) that is loaded into the counter. When the counter reaches the end of the count, a timer interrupt request, IRQ4 (T0) or IRQ5 (T1), is generated. The counters are programmed to START, STOP, restart to CONTINUE, or restart from the initial value. The counters can also be programmed to STOP upon reaching 0 (SINGLE-PASS mode) or to automatically reload the initial value and continue counting (MODULO-N CONTINUOUS mode). The counters, but not the prescalers, are read at any time without disturbing their value or count mode. The clock source for T1 is user-definable and is either the internal microprocessor clock divide-by-four, or an external signal input through Port 3. The Timer Mode Register configures the external timer input (P31) as an external clock, a trigger input that is retriggerable or nonretriggerable, or as a gate input for the internal clock. The counter/timers are cascaded by connecting the T0 output to the input of T1. TIN mode is enabled by setting PRE1 bit D1 to 0.
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Expanded Register Bank 0h Working Register Group F REGISTER POINTER 7 6 5 4 3 2 1 0 FF FE FD Working Register Group Pointer Expanded Register File Pointer FC FB FA F9 F8 F7* F6* Z8 Working Register File FFh F0h F5 F4 F3 F2 F1 F0 SPL SPH RP FLAGS IMR IRQ IPR P01M P3M P2M PRE0 T0 PRE1 T1 TMR Reserved
RESET CONDITION 7 0 0 0 0 0 0 0 1 6 0 0 0 5 0 0 0 4 0 0 0 3 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0
XXXXXXXX XXXXXXX 0 1 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 0 0 0 1 0 1 0 1
XXXXXXXX
XXXXXXX0 XXXXXXXX XXXXXX0 0 0 0 0 0 0 0 0 0 XXXXXXXX
Expanded Register Bank (Fh) Working Register Group 0 70h (F) 0F* (F) 0E (F) 0D* (F) 0C (F) 0B** (F) 0A (F) 09 (F) 08 0Fh 00h (F) 07 (F) 06 (F) 05 (F) 04 (F) 03 (F) 02 (F) 01 (F) 00* Notes X - Indeterminate * - Is not reset via Stop-Mode Recovery ** - Is not reset via Stop-Mode Recovery, except for bit D0 WDTMR Reserved SMR2 Reserved SMR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PCON 0
RESET CONDITION XXX0 1 1 0 1 0 0
XXXXXX0 0 1 0 0 0 0
UUUUUUUU
Figure 9.Expanded Register File Architecture
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OSC
D1 SMR /2 /4 6-Bit Down Counter PRE0 Initial Value Register Write Write 8-Bit Down Counter T0 Initial Value Register Read T0 Current Value Register IRQ4
D0 SMR
16
Internal Data Bus Internal Clock External Clock Clock Logic /4 /2
TOUT P36
6-Bit Down Counter PRE1 Initial Value Register Write Write
8-Bit Down Counter T1 Initial Value Register Read T1 Current Value Register
IRQ5
Internal Clock Gated Clock Triggered Clock TIN P31
Internal Data Bus
Figure 10.Counter/Timer Block Diagram Interrupts. The Z8 features six different interrupts from six different sources.
These interrupts are maskable and prioritize. The six sources are divided as follows: four sources are claimed by Port 3 lines P33-P30, and two are claimed by counter/timers (Interrupt Types, Sources, and Vectors). The Interrupt Mask Register globally or individually enables or disables the six interrupt requests.
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Table 5. Interrupt Types, Sources, and Vectors Name IRQ0 IRQ1, IRQ2 IRQ3 IRQ4 IRQ5 Source IRQ0 IRQ1 IRQ2, TIN IRQ3 T0 T1 Vector Location 0,1 2,3 4,5 6,7 8,9 10,11 Comments External (P32), Rising and Falling Edges Triggered External (P33), Falling Edge Triggered External (P31), Rising and Falling Edges Triggered External (P30), Falling Edge Triggered Internal Internal
IRQ0 IRQ1,3,4,5
IRQ2
Interrupt Edge Select
IRQ (D6, D7)
IRQ
IMR 6 IPR
Global Interrupt Enable Interrupt Request
Priority Logic
Vector Select
Figure 11.Interrupt Block Diagram
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When more than one interrupt is pending, priorities are resolved by a programmable priority encoder that is controlled by the Interrupt Priority register. An interrupt machine cycle activates when an interrupt request is granted. This action disables all subsequent interrupts, saves the Program Counter and Status Flags, and then branches to the program memory vector location reserved for that interrupt. All Z8 interrupts are vectored through locations in the program memory. This memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request. To accommodate polled interrupt systems, interrupt inputs are masked and the Interrupt Request register is polled to determine which of the interrupt requests require service. When in ANALOG mode, an interrupt resulting from AN1 maps to IRQ2, and an interrupt from AN2 maps to IRQ0. Interrupts IRQ2 and IRQ0 may be rising, falling, or both edge-triggered, and are programmed in the IRQ register. The software polls to identify the state of the pin. When in ANALOG mode, IRQ1 is generated by the Stop-Mode Recovery source selected by SMR Register bits D4, D3, D2, or SMR2 D1 or D0. Programming bits for the Interrupt Edge Select are located in the IRQ register, bits D7 and D6. The configuration is indicated in Table 7.
Table 6. IRQ Register* IRQ D7 0 D6 0 1 1 1
Notes: F = Falling Edge R = Rising Edge
Interrupt Edge P31 F F R R/F P32 F R F R/F
0 1
Clock. The Z8 on-chip oscillator features a high-gain, parallel-resonant amplifier
for connection to a crystal, LC, RC, ceramic resonator, or any suitable external clock source (XIN = INPUT, XOUT = OUTPUT). The crystal should be AT-cut, 4 MHz maximum, with a series resistance (RS) of less than or equal to 100 when oscillating from 1MHz to 4MHz. The crystal should be connected across XTAL1 and XTAL2 using the vendor's recommended capacitor values from each pin directly to the device Ground pin to reduce ground-noise injection into the oscillator. The RC oscillator option is mask-
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programmable and is selectable by the customer at the time the ROM code is submitted. Notes: The RC option is available up to 4MHz. The RC oscillator configuration must be an external resistor connected from XIN to XOUT, with a frequency-setting capacitor from XIN to Ground (Figure 12). For better noise immunity, the capacitors should be tied directly to the device Ground pin (VSS).
XTAL1 C1 ** XTAL2 C2 VSS** Ceramic Resonator or Crystal C1, C2 = 47fd* f = 4MHz C2 VSS** LC Clock C1, C2 = 22 pf L =130 H* f = 3 MHz* C1 ** L
XTAL1
XTAL1 C VSS** R
XTAL1
XTAL2
XTAL2
XTAL2
External Clock
RC Clock @5V VCC (TYP) C1 = 44pF* R = 4K ohm f = 3 MHz*
*Preliminary value, including pin parasitics ** Device Ground Pin
Figure 12.Oscillator Configuration Power-On Reset (POR). A timer circuit clocked by a dedicated on-board RC oscillator is used for the Power-On Reset (POR) timer function. The POR time allows VCC and the oscillator circuit to stabilize before instruction execution begins.
The POR timer circuit is a one-shot timer triggered by one of three conditions: 1. Power fail to Power OK status. 2. Stop-Mode Recovery (if D5 of SMR = 1). 3. WDT time-out. The POR time is specified as TPOR. Bit 5 of the Stop-Mode Register determines whether the POR timer is bypassed after Stop-Mode Recovery (typical for external clock, RC/LC oscillators).
HALT. HALT turns off the internal CPU clock, but not the CRYSTAL oscillation.
The counter/timers, analog comparators, and external interrupts IRQ0, IRQ1, IRQ2, and IRQ3 remain active. The devices are recovered by interrupts and are either externally or internally generated. This also includes WDT time-out Reset
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and VLV Reset. An interrupt request must be enabled and executed to exit HALT mode. After the interrupt service routine, the program continues from the instruction after the HALT. In order to enter STOP (or HALT) mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. The user must execute a NOP (Op Code = FFh) immediately before the appropriate sleep instruction. For example:
FF 6F NOP ; clear the pipeline
STOP ; enter STOP mode
or
FF 7F NOP ; clear the pipeline
HALT ; enter HALT mode
STOP. This instruction turns off the internal clock and external crystal oscillation.
The STOP instruction also reduces the standby current to 10 A or less. The analog comparators are automatically powered down in STOP-Mode. STOP mode is terminated either by WDT time-out, POR, Stop-Mode Recovery, or any Reset. As a result, the processor restarts the application program at address 000Ch. A WDT time-out in STOP mode affects all registers the same as if a Stop-Mode Recovery occurred via a selected Stop-Mode Recovery source except that the POR delay is enabled even if the delay is selected for disable. Note: If a permanent WDT is selected, the WDT runs in all modes and cannot be stopped or disabled if the onboard RC oscillator is selected to drive the WDT.
Port Configuration Register (PCON). The PCON register configures the ports individually; comparator output on Port 3, open-drain on Port 0, low EMI on Ports 0, 2, and 3, and low-EMI oscillator. The PCON register is located in the expanded register file at Bank F, location 00h (Table 8).
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Table 7. Port Configuration Register--PCON 00h/R0 Bank Fh: WRITE ONLY Bit R/W Reset D7 W 1 D6 W 1 D5 W 1 D4 W 1 D3 W 1 D2 W 1 D1 W 1 D0 W 0
Note: R = Read, W = Write, X = Indeterminate.
Bit Position D7
Bit Field Oscillator
R/W W
Reset State Description 1 Low-EMI Oscillator 0: Low EMI 1: Standard Port 3 0: Low EMI 1: Standard Port 2 0: Low EMI 1: Standard Reserved* 1: Must be "1" Port 0* 0: Low EMI 1: Standard Port 0 0: Open-Drain 1: Push-Pull Active Reserved* 1: Must be "1" Port 3 Comparator Output 0: P34, P37 Standard Output 1: P34, P37 Comparator Output
D6
Port 3 I/O
W
1
D5
Port 2 I/O
W
1
D4 D3
Reserved Port 0 I/O
W W
1 1
D2
Port 0 I/O
W
1
D1 D0
Reserved Port 3
W W
1 0
Comparator Output Port 3 (D0). Bit 0 controls the comparator use in Port 3. A 1 in this location brings the comparator outputs to P34 and P37, and a 0 releases the Port to its standard I/O configuration. The default value is 0. Port 0 Open-Drain (D2). Port 0 is configured as an open-drain by resetting this bit
(D2 = 0) or configured as push-pull active by setting this bit (D2 = 1). The default value is 1.
Low-EMI Port 0 (D3). Port 0 is configured as a low-EMI port by resetting this bit (D3
= 0) or configured as a Standard Port by setting this bit (D3 = 1). The default value is 1.
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Low-EMI Port 2 (D5). Port 2 is configured as a low-EMI port by resetting this bit (D5
= 0) or configured as a Standard Port by setting this bit (D5 = 1). The default value is 1.
Low-EMI Port 3 (D6). Port 3 is configured as a low-EMI port by resetting this bit (D6
= 0) or configured as a Standard Port by setting this bit (D6 = 1). The default value is 1.
Low-EMI OSC (D7). This bit of the PCON register controls the low-EMI noise oscillator. A 1 in this location configures the oscillator, DS, AS and R/W with standard drive, while a 0 configures the oscillator, DS, AS and R/W with low noise drive. LOW-EMI mode reduces the drive of the oscillator (OSC). The default value is 1.
Note: Maximum external clock frequency of 4 MHz when running in LOW-EMI OSCILLATOR mode.
Low-EMI Emission. The Z8 is programmed to operate in a low-EMI emission mode
in the PCON register. The oscillator and all I/O ports is programmed as LOW-EMI EMISSION mode independently. Use of this feature results in:
* * * *
The pre-drivers slew rate reduced to 10 ns (typical) Low-EMI output drivers exhibit resistance of 200 (typical) Low-EMI Oscillator Internal SCLK = XIN operation limited to a maximum of 4 MHz-250 ns cycle time, when LOW EMI OSCILLATOR is selected and system clock (SMR Register Bit D1 = 1)
Stop-Mode Recovery Registers (SMR1 and SMR2). These registers select the clock
divide value and determine the mode of Stop-Mode Recovery (Tables 8 and 11). All bits are WRITE ONLY, except bit 7 of SMR1, which is READ ONLY. SMR1 bit 7 is a flag bit that is set by hardware on a Stop-Mode Recovery condition and reset by a power-on cycle. For SMR1, bit 6 controls whether a Low level or a High level is required from the recovery source. Bit 5 controls the reset delay after StopMode Recovery. Bits 2, 3, and 4 of the SMR1 register specify the source of the Stop-Mode Recovery signal. Bits 0 and 1 determine the time-out period of the WDT. The SMR registers are located in Bank F of the Expanded Register File at addresses 0Bh and 0Dh, respectively. For SMR2, bits 7 to 2 are reserved. Bits 1 and 0 of the SMR2 register specify the source of the Stop-Mode Recovery signal.
Table 8. Stop-Mode Recovery Register 1--SMR1 0Bh/R11 Bank Fh: WRITE ONLY, except Bit D7, which is READ ONLY Bit R/W D7 R D6 W D5 W D4 W D3 W D2 W D1 W D0 W
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Table 8. Stop-Mode Recovery Register 1--SMR1 0Bh/R11 Bank Fh: WRITE ONLY, except Bit D7, which is READ ONLY Reset 0 0 1 0 0 0 0 0
Note: R = Read, W = Write, X = Indeterminate.
Bit Position D7
Bit Field STP
R/W R
Reset State Description 0 Stop Flag 0: POR 1: Stop-Mode Recovery Stop-Mode Recovery Level 0: Low 1: High Stop Delay 0: Off 1: On Stop-Mode Recovery Source 1 000: POR only and/or external RESET 001: P30 010: P31 011: P32 100: P33 101: P27 110: P2 NOR 0-3 111: P2 NOR 0-7 External Clock Divide-by-2 0: SCLK & TCLK = XTAL / 2 1: SCLK & TCLK = XTAL SCLK & TCLK Divide-by-16 0: Off 2 1: On
D6
SMR
W
0
D5
STPDLY
W
1
D4-D2
SMRSRC
W
000
D1
EXTCLK
W
0
D0
CLK
W
0
Notes: 1. Do not use in conjunction with SMR2 Source. 2. Cleared by RESET and SMR.
SCLK & TCLK Divide-by-16 Select (D0). Bit D0 of the SMR controls a divide-by-16
prescaler of SCLK & TCLK. The purpose of this control is to selectively reduce device power consumption during normal processor execution (SCLK control) and/or HALT mode (where TCLK sources counter/timers and interrupt logic). This bit is reset to D0 = 0 after a Stop-Mode Recovery.
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External Clock Divide-by-Two (D1). This bit can eliminate the oscillator divide-bytwo circuitry. When this bit is 0, the system clock (SCLK) and timer clock (TCLK) are equal to the external clock frequency divided by 2. The SCLK is equal to the external clock frequency when this bit is set (D1 = 1). Using this bit together with D7 of PCON further helps lower EMI (that is, D7 (PCON) = 0, D1 (SMR) = 1). The default setting is 0. Maximum external clock frequency is 4 MHz when SMR bit D1 = 1 where SCLK & TCLK = XIN. Stop-Mode Recovery Source (D2, D3, and D4). These three bits of the SMR specify
the wake-up source of the Stop-Mode Recovery (Figure and Stop-Mode Recovery Source). When the Stop-Mode Recovery Sources are selected in this register, then SMR2 register bits D0,D1 must be set to 0. Note: If the Port 2 pin is configured as an output, this output level is read by the SMR circuitry.
VDD D1 D0 00 SMR2 D1 D0 SMR2 0 1 P20 P23 P20 P27 D1 D0 10
SMR2
VDD D4 D3 D2 0 00 SMR P30 P31 P32
D4 D3 D2 D4 D3 D2 D4 D3 D2 SMR 0 0 0 SMR 1 0 0 SMR 1 0 1 0 10 0 11 P20 P33 P27 P23
D4 D3 D2 SMR 1 1 0 P20
SMR
D4 D3 D2 1 11
P27 To POR RESET M U X
Stop-Mode Recovery Edge Select (SMR)
P33 From Pads
To P33 Data Latch and IRQ1
Digital/Analog Mode Select (P3M)
Figure 13.Stop-Mode Recovery Source
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Table 9. Stop-Mode Recovery Source SMR[4-2] D4 0 0 0 0 1 1 1 1 D3 0 0 1 1 0 0 1 1 D2 0 1 0 1 0 1 0 1 Operation/Description of Action POR and/or external reset recovery P30 transition P31 transition (not in ANALOG mode) P32 transition (not in ANALOG mode) P33 transition (not in ANALOG mode) P27 transition Logical NOR of P20 through P23 Logical NOR of P20 through P27
Stop-Mode Recovery Delay Select (D5). This bit, if High, enables the TPOR RESET
delay after Stop-Mode Recovery. The default configuration of this bit is 1. If the fast wake up (no delay) is selected, the Stop-Mode Recovery source must be kept active for at least 5 TPC. The clock source must be RC/LC/external clock driven.
Stop-Mode Recovery Edge Select (D6). A 1 in this bit position indicates that a high
level on any one of the recovery sources wakes the Z8 from STOP mode. A 0 indicates low-level recovery. The default is 0 on POR (Table 11). This bit is used for either SMR or SMR2.
Cold or Warm Start (D7). This bit is set by the device upon entering STOP mode. A
0 in this bit (cold) indicates that the device resets by POR/WDT RESET. A 1 in this bit (warm) indicates that the device awakens by a Stop-Mode Recovery source. Note: If the Port 2 pin is configured as an output, this output level is read by the SMR2 circuitry.
Stop-Mode Recovery Register 2 (SMR2). This register contains additional Stop-
Mode Recovery sources. When the Stop-Mode Recovery sources are selected in this register then SMR register bits D2, D3, and D4 must be 0.
Table 10. Stop-Mode Recovery Register 2 SMR1-0 D1 0 D0 0 Operation/Description of Action POR and/or external reset recovery
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Table 10. Stop-Mode Recovery Register 2 SMR1-0 D1 0 1 D0 1 0 Operation/Description of Action Logical AND of P20 through P23 Logical AND of P20 through P27
Table 11. Stop-Mode Recovery Register 2--SMR2 0Dh/R13 Bank Fh: WRITE ONLY Bit R/W Reset D7 W X D6 W X D5 W X D4 W X D3 W X D2 W X D1 W 0 D0 W 0
Note: R = Read, W = Write, X = Indeterminate.
Bit/ Field
Bit Position
R/W W W
Reset State Description X 00 Reserved--must be 0 Stop-Mode Recovery Source 2* 00: POR only 01: AND P20, P21, P22, P23 10: AND P20, P21, P22, P23, P24, P25, P26, P27 11: Reserved
D7-D2 Reserved D1-D0 STOP Mode
Note: *Do not use in conjunction with SMR Source.
Watch-Dog Timer Mode Register (WDTMR). The WDT is a retriggerable one-shot
timer that resets the Z8 if it reaches its terminal count. The WDT is initially enabled by executing the WDT instruction and refreshed on subsequent executions of the WDT instruction. The WDT circuit is driven by an onboard RC oscillator or external oscillator from the XIN pin. The POR clock source is selected with bit 4 of the WDT register (Table 15). WDT instruction affects the Z (Zero), S (Sign), and V (Overflow) flags. The WDTMR must be written to within the first 60 internal system clocks. After that, the WDTMR is WRITE-protected. Note: WDT time-out while in STOP mode does not reset SMR, PCON, WDTMR, P2M, P3M, Ports 2 & 3 Data Registers, but the POR delay counter is still enabled even though the SMR stop delay is disabled.
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Table 12. Watch-Dog Timer Mode Register--WDTMR 0Fh/R15: WRITE ONLY Bit R/W Reset D7 W X D6 W X D5 W X D4 W 0 D3 W 1 D2 W 1 D1 W 0 D0 W 1
Note: R = Read, W = Write, X = Indeterminate.
Bit/ Field
Bit Position
R/W W W
Reset State Description X 0 Reserved--must be 0 XIN/INT RC Select for WDT 0: On-Board RC 1: XIN WDT During STOP WDT During HALT WDT Tap Int RC OSC 00: 3.5 ms 01: 7.0 ms 10: 14.0 ms 11: 56.0 ms System Clock 128 SCLK 256 SCLK 512 SCLK 2048 SCLK
D7-D5 Reserved D4 XIN
D3 D2
WDT WDT
W W W
1 1 01
D1-D0 WDT Tap
Note: Not used in conjunction with SMR Source.
WDT Time Select (D0,D1). Selects the WDT time period and is configured as indi-
cated in Table 14.
Table 13. WDT Time Select D1 0 0 1 1 D0 0 1 0 1 Timeout of Internal RC OSC 3.5 ms min 7 ms min 14 ms min 56 ms min Timeout of System Clock 128 SCLK 256 SCLK 512 SCLK 2048 SCLK
Note: SCLK = system bus clock cycle. The default on RESET is 7 ms. Values provided are for VCC = 5.0V.
WDTMR During HALT (D2). This bit determines whether or not the WDT is active
during HALT mode. A 1 indicates active during HALT. The default is 1.
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WDTMR During STOP (D3). This bit determines whether or not the WDT is active
during STOP mode. Because the XIN clock is stopped during STOP mode, the onboard RC must be selected as the clock source to the POR counter. A 1 indicates active during STOP. The default is 1. Note: If the permanent WDT programming option is selected, the WDT runs in all modes and cannot be stopped or disabled if the on board RC oscillator is selected as the clock source for WDT.
Clock Source for WDT (D4). This bit determines which oscillator source is used to
clock the internal POR and WDT counter chain. If the bit is a 1, the internal RC oscillator is bypassed and the POR and WDT clock source is driven from the external pin, XIN. The default configuration of this bit is 0 which selects the internal RC oscillator.
WDTMR Register Accessibility. The WDTMR register is accessible only during the
first 64 internal system clock cycles from the execution of the first instruction after Power-On Reset, Watch-Dog Reset, or Stop-Mode Recovery. After this point, the register cannot be modified by any means, intentional or otherwise. The WDTMR cannot be read and is located in Bank Fh of the Expanded Register File at address location 0Fh (Figure 14). Note: The WDT is permanently enabled (automatically enabled after RESET) through a programmable option. The option is selected when the device is programmed. In this mode, WDT is always activated when the device comes out of RESET. Execution of the WDT instruction serves to refresh the WDT time-out period. WDT operation in the HALT and STOP modes is controlled by WDTMR programming. If this option is not selected when the device is programmed, the WDT must be activated by the user through the WDT instruction and is always disabled by any reset to the device.
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Reset
4 Clock Filter
Clear CLK
18 Clock RESET Generator RESET
hhh
RESET Internal RESET
Intern II
WDT Select (WDTMR) Clock Source Select (WDTMR) XTAL Internal RC OSC VDD VLV WDT WDT WWW From Stop Mode Recovery Source Stop Delay Select (SMR) + VLV Operating Voltage Det. M U X
WDT TAP SELECT
7ms POR 3.5ms 7ms 14ms 56ms CK WDT/POR Counter Chain CLK
bbbmc
cbcbb
Figure 14.Resets and Watch-Dog Timer Example
Voltage Comparator
Low-Voltage Protection. An onboard Voltage Comparator checks that VCC is at the
required level to ensure correct operation of the device. RESET is globally driven if VCC is below the specified voltage (Low-Voltage Protection). The minimum operating voltage varies with the temperature and operating frequency, while the LowVoltage Protection (VLV) varies with temperature only. The Low-Voltage Protection trip voltage (VLV) is less than VLV maximum and more than 1.4V under the following conditions. At 25C, the device functions normally at or above 3.0V. Below 3.0V, the device functions normally until the Low-Voltage Protection trip point (VLV) is reached for the temperatures and operating frequencies in Table 15. The device is guaranteed to function normally at supply voltages above the Low-Voltage Protection trip
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point. The actual Low-Voltage Protection trip point is a function of temperature and process parameters (Figure 15).
VCC (Volts) 3.80
3.60
3.40 3.20 3.00 VLV (Typical) 2.80 2.60 2.40 Temp +80 +100 +120 +140
-60
-40
-20
0
+20
+40
+60
Figure 15.Typical Low-Voltage Protection vs. Temperature Table 14. Maximum (VLV) Conditions: Internal Clock Frequency equal or less than 4 MHz
Note: The internal clock frequency relationship to the CRYSTAL clock is dependent on SMR Bit 0 1 setting.
Control Registers
The Z87233 offers 2 banks of registers, as detailed in the following pages.
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Expanded Register File, Bank 0h
Bank 0h of the Expanded Register File contains 15 Control registers that perform the Timer, Prescaler, Port, Interrupt, Flag, and Pointer functions, as shown in Tables 16 through 30. Table 15 lists the reset states of all 15 Bank 0h Control registers.
Table 15. Expanded Register File Registers--Reset States D7 F0h F1h F2h F3h F4h F5h F6h F7h F8h F9h FAh FBh FCh FDh FEh FFh Reserved TMR T1 PRE1 T0 PRE0 P2M* P3M* P01M IPR IRQ IMR FLAGS RP SPH SPL 0 X X X X 1 0 0 X 0 0 X 0 0 0 0 X X X X 1 0 1 X 0 X X 0 0 0 0 X X X X 1 0 0 X 0 X X 0 0 0 0 X X X X 1 0 0 X 0 X X 0 0 0 0 X X X X 1 0 1 X 0 X X 0 0 0 0 X X X X 1 0 1 X 0 X X 0 0 0 0 X 0 X X 1 0 0 X 0 X X 0 0 0 0 X 0 X 0 1 0 1 X 0 X X 0 0 0 D6 D5 D4 D3 D2 D1 D0
Note: *Not reset with a Stop-Mode Recovery.
Timer Mode Register
The Timer Mode Register, TMR, controls timing and counter functions. READ/ WRITE and reset states for bits D7-D0 are listed in Table 16.
Table 16. Timer Mode Register--TMR F1h/R241 Bank 0h: READ/WRITE Bit R/W D7 R/W D6 R/W D5 R/W D4 R/W D3 R/W D2 R/W D1 R/W D0 R/W
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Z87233 CMOS Z8" MCU Consumer Controller Processor
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Table 16. Timer Mode Register--TMR F1h/R241 Bank 0h: READ/WRITE Reset State 0 0 0 0 0 0 0 0
Note: R = Read, W = Write.
Bit Position D7-D6
Bit Field TOUT Mode
R/W R/W
Reset State Description 00 TOUT Mode 00: Off 01: T0 Output 10: T1 Output 11: Internal Clock Output TIN Mode 00: External Clock Input 01: Gate Input 10: Trigger Input (nonretriggerable) 11: Trigger Input (retriggerable) T1 Count 0: Disable 1: Enable T1 0: No Function 1: Load T1 T0 Count 0: Disable 1: Enable T0 0: No Function 1: Load T0
D5-D4
TIN Mode
R/W
00
D3
T1 Count
R/W
0
D2
T1
R/W
0
D1
T0 Count
R/W
0
D0
T0
R/W
0
Counter/Timer 1 Register The Counter/Timer 1 Register, T1, controls timing and counter functions. READ/ WRITE and reset states for bits D7-D0 are listed in Table 17.
Table 17. Counter/Timer 1 Register--T1 F2h/R242 Bank 0h: READ/WRITE Bit R/W Reset State D7 R/W X D6 R/W X D5 R/W X D4 R/W X D3 R/W X D2 R/W X D1 R/W X D0 R/W X
Note: R = Read, W = Write, X = Indeterminate.
PS022701-0104
Z87233 CMOS Z8" MCU Consumer Controller Processor
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Bit Position D7-D0
Bit Field T1
R/W R W
Reset State Description X X T1 Current Value T1 Automatic Reload Value Range = 1-256 decimal; 01h-00h
Prescaler 1 Register The Prescaler 1 Register, PRE1, controls clocking functions. READ/WRITE and reset states for bits D7-D0 are listed in Table 18.
Table 18. Prescaler 1 Register--PRE1 F3h/R243 Bank 0h: WRITE ONLY Bit R/W Reset State D7 W X D6 W X D5 W X D4 W X D3 W X D2 W X D1 W 0 D0 W 0
Note: W = Write, X = Indeterminate.
Bit Position D7-D2 D1
Bit Field Prescaler Clock
R/W W W
Reset State Description X 0 Prescaler Modulo Range = 1-64 decimal; 01h-00h Clock Source 0: T1 External Timing Input (TIN) Mode 1: T1 Internal Count Mode 0: T1 Single Pass 1: T1 Modulo N
D0
Count
W
0
Counter/Timer 0 Register The Counter/Timer 0 Register, T0, controls timing and counter functions. READ/ WRITE and reset states for bits D7-D0 are listed in Table 19.
Table 19. Counter/Timer 0 Register--T0 F4h/R244 Bank 0h: READ/WRITE Bit R/W Reset State D7 R/W X D6 R/W X D5 R/W X D4 R/W X D3 R/W X D2 R/W X D1 R/W X D0 R/W X
Note: R = Read, W = Write, X = Indeterminate.
PS022701-0104
Z87233 CMOS Z8" MCU Consumer Controller Processor
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Bit Position D7-D0
Bit Field T0
R/W R W
Reset State Description X X T0 Current Value T0 automatic Reload Value Range = 1-256 decimal; 01h - 00h
Prescaler 0 Register The Prescaler 0 Register PRE0 controls clocking functions. WRITE and reset states for bits D7-D0 are listed in Table 20.
Table 20. Prescaler 0 Register--PRE0 F5h/R245 Bank 0h: WRITE ONLY Bit R/W Reset State D7 W X D6 W X D5 W X D4 W X D3 W X D2 W X D1 W X D0 W 0
Note: W = Write, X = Indeterminate.
Bit Position D7-D2 D1 D0
Bit Field Prescaler Reserved Count
R/W W W W
Reset State Description X X 0 Prescaler Modulo Range = 1-64 decimal; 01h-00h Reserved--must be 0 Count Mode 0: T0 Single Pass 1: T0 Modulo N
Port 2 Mode Register The Port 2 Mode Register, P2M, controls Port 2 I/O functions. WRITE and reset states for bits D7-D0 are listed in Table 21.
Table 21. Port 2 Mode Register--P2M F6h/R246 Bank 0h: WRITE ONLY Bit R/W Reset State
Note: W = Write.
D7 W 1
D6 W 1
D5 W 1
D4 W 1
D3 W 1
D2 W 1
D1 W 1
D0 W 1
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Z87233 CMOS Z8" MCU Consumer Controller Processor
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Bit Position D7-D0
Bit Field P20-P27
R/W W
Reset State Description 1 P20-P27 I/O Definition 0: Defines bit as Output 1: Defines bit as Input
Port 3 Mode Register The Port 3 Mode Register P3M controls Port 3 I/O functions. WRITE and reset states for bits D7-D0 are listed in Table 22.
Table 22. Port 3 Mode Register--P3M F7h/R247 Bank 0h: WRITE ONLY Bit R/W Reset State
Note: W = Write.
D7 W 0
D6 W 0
D5 W 0
D4 W 0
D3 W 0
D2 W 0
D1 W 0
D0 W 0
Bit Position D7-D2 D1
Bit Field Reserved Port 3
R/W W W
Reset State Description 00 0 Reserved--must be 00 Port 3 0: P31, P32 DIGITAL mode 1: P31, P32 ANALOG mode Port 2 0: Open-Drain 1: Push-Pull
D0
Port 2
W
0
Ports 0 and 1 Mode Register The Ports 0 and 1 Mode Register, P01M, controls port and timing functions for Ports 0 and 1. WRITE and reset states for bits D7-D0 are listed in Table 23.
Table 23. Ports 0 and 1 Mode Register--P01M F8h/R248 Bank 0h: WRITE ONLY Bit R/W Reset State
Note: W = Write.
D7 W 0
D6 W 1
D5 W 0
D4 W 0
D3 W 1
D2 W 1
D1 W 0
D0 W 1
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Z87233 CMOS Z8" MCU Consumer Controller Processor
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Bit Position D7 D6
Bit Field Reserved P04-P07
R/W W W
Reset State Description 0 01 Reserved - Must be 0 P04-P07 Mode* 0: Output 1: Input External Memory Timing Reserved - Must be 0 P10-P17 Mode* 00: Reserved - Must be 0 Stack Selection* 0: Reserved 1: Must be "1" Reserved - Must be 0 P00-P03 Mode* 0: Output 1: Input
D5 D4-D3 D2
Reserved Reserved Stack
W W W
0 01 1
D1 D0
Reserved P00-P03
W W
0 1
Interrupt Priority Register The Interrupt Priority Register, IPR, prioritizes interrupt functions. WRITE and reset states for bits D7-D0 are listed in Table 24.
Table 24. Interrupt Priority Register--IPR F9h/R249 Bank 0h: WRITE ONLY Bit R/W Reset State D7 W X D6 W X D5 W X D4 W X D3 W X D2 W X D1 W X D0 W X
Note: W = Write, X = Indeterminate.
Bit Bit Position Field D7-D6 D5 Reserved IRQ3, IRQ5
R/W W W
Reset State Description XX X Reserved--must be 0 IRQ3, IRQ5 Priority (Group A) 0: IRQ5 > IRQ3 1: IRQ3 > IRQ5
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Z87233 CMOS Z8" MCU Consumer Controller Processor
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Bit Bit Position Field D4,D3,D0 Interrupt
R/W W
Reset State Description XXX Interrupt Group Priority 000: Reserved 001: C > A > B 010: A > B > C 011: A > C > B 100: B > C > A 101: C > B > A 110: B > A > C 111: Reserved IRQ0, IRQ2 Priority (Group B) 0: IRQ2 > IRQ0 1: IRQ0 > IRQ2 IRQ1, IRQ4 Priority (Group C) 0: IRQ1 > IRQ4 1: IRQ4 > IRQ1
D2
IRQ0, IRQ2
W
X
D1
IRQ1, IRQ4
W
X
Interrupt Request Register The Interrupt Request Register, IRQ, controls interrupt functions. READ/WRITE and reset states for bits D7-D0 are listed in Table 25.
Table 25. Interrupt Request Register--IRQ FAh/R250 Bank 0h: READ/WRITE Bit R/W Reset D7 R/W 0 D6 R/W 0 D5 R/W 0 D4 R/W 0 D3 R/W 0 D2 R/W 0 D1 R/W 0 D0 R/W 0
Note: R = Read, W = Write.
Bit Position D7-D6
Bit Field Interrupt Edge
R/W R/W
Reset State Description 00 Interrupt Edge 00: P31 P32 01: P31 P32 10: P31 P32 11: P31 P32 Interrupt IRQ5 = T1 0: No Interrupt pending 1: Interrupt pending
D5
IRQ5
R/W
0
PS022701-0104
Z87233 CMOS Z8" MCU Consumer Controller Processor
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Bit Position D4
Bit Field IRQ4
R/W R/W
Reset State Description 0 Interrupt IRQ4 = T0 0: No Interrupt pending 1: Interrupt pending Interrupt IRQ3 = P30 Input 0: No Interrupt pending 1: Interrupt pending Interrupt IRQ2 = P31 Input 0: No Interrupt pending 1: Interrupt pending Interrupt IRQ1 = P33 Input 0: No Interrupt pending 1: Interrupt pending Interrupt IRQ0 = P32 Input 0: No Interrupt pending 1: Interrupt pending
D3
IRQ3
R/W
0
D2
IRQ2
R/W
0
D1
IRQ1
R/W
0
D0
IRQ0
R/W
0
Interrupt Mask Register The Interrupt Mask Register, IMR, controls interrupt functions. READ/WRITE and reset states for bits D7-D0 are listed in Table 26.
Table 26. Interrupt Mask Register--IMR FBh/R251 Bank 0h: READ/WRITE Bit R/W Reset D7 R/W 0 D6 R/W X D5 R/W X D4 R/W X D3 R/W X D2 R/W X D1 R/W X D0 R/W X
Note: R = Read, W = Write, X = Indeterminate.
PS022701-0104
Z87233 CMOS Z8" MCU Consumer Controller Processor
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Bit Position D7
Bit Field MIE
R/W R/W
Reset State Description 0 Master Interrupt Enable 1: Enable interrupts 0: Disable interrupts RAM Protect 1: Enable RAM Protect* 0: Disable RAM Protect Interrupt Request 1: Enable IRQ0-IRQ5 0: Disable IRQ0-IRQ5
D6
RAM Protect
R/W
X
D5-D0
IRQ5-IRQ0
R/W
X
Note: * Must select RAM Protect Mask Option
Flags Register The CPU sets flags in the Flags Register, FLAGS, to allow the user to perform tests based on differing logical states. READ/WRITE and reset states for bits D7- D0 are listed in Table 27.
Table 27. Flags Register--FLAGS FCh/R252 Bank 0h: READ/WRITE Bit R/W Reset D7 R/W X D6 R/W X D5 R/W X D4 R/W X D3 R/W X D2 R/W X D1 R/W X D0 R/W X
Note: R = Read, W = Write, X = Indeterminate.
Bit Position D7 D6 D5 D4 D3 D2 D1 D0
Bit Field Carry Zero Sign Overflow Decimal Adjust Half Carry User User
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset State X X X X X X X X
Description Carry Flag Zero Flag Sign Flag Overflow Flag Decimal Adjust Flag Half Carry Flag User Flag F2* User Flag F1*
Note: *Not affected by RESET.
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Z87233 CMOS Z8" MCU Consumer Controller Processor
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Register Pointer Register The Register Pointer Register, RP, controls pointer functions in the working registers. READ/WRITE and reset states for bits D7-D0 are listed in Table 28.
Table 28. Register Pointer--RP FDh/R253 Bank 0h: READ/WRITE Bit R/W Reset D7 R/W 0 D6 R/W 0 D5 R/W 0 D4 R/W 0 D3 R/W 0 D2 R/W 0 D1 R/W 0 D0 R/W 0
Note: R = Read, W = Write.
Bit Position D7-D4
Bit Field Working Register Pointer Expanded Register File Bank
R/W R/W
Reset State Description 0 Working Register Pointer
D3-D0
R/W
0
Expanded Register File Bank
General Purpose Register The General Purpose Register (GPR) READ/WRITE and reset states for bits D7- D0 are listed in Table 29.
Table 29. General Purpose--GPR FEh/R254 Bank 0h: READ/WRITE Bit R/W Reset D7 R/W 0 D6 R/W 0 D5 R/W 0 D4 R/W 0 D3 R/W 0 D2 R/W 0 D1 R/W 0 D0 R/W 0
Note: R = Read, W = Write.
Bit Position D7-D0
Bit Field GPR
R/W R/W
Reset State Description 0 General Purpose Register (D7-D0)
Stack Pointer Low Register The Stack Pointer Low Register, SPL, controls pointer functions in the lower byte. READ/WRITE and reset states for bits D7-D0 are listed in Table 30.
PS022701-0104
Z87233 CMOS Z8" MCU Consumer Controller Processor
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Table 30. Stack Pointer Low--SPL FFh/R255 Bank 0h: READ/WRITE Bit R/W Reset D7 R/W 0 D6 R/W 0 D5 R/W 0 D4 R/W 0 D3 R/W 0 D2 R/W 0 D1 R/W 0 D0 R/W 0
Note: R = Read, W = Write.
Bit Position D7-D0
Bit Field SPL
R/W R/W
Reset State Description 0 Stack Pointer Lower Byte (SP7-SP0)
Expanded Register File, Bank Fh
Expanded Register File Bank Fh contains 4 registers that perform the Port Configuration, Stop-Mode Recovery, and Watch-Dog Timer Mode functions, as shown in Tables 31 through 35. These 4 registers are not reset by a Stop-Mode Recovery. Table 31 lists the reset states of all 4 Bank Fh registers.
Table 31. Expanded Register File Registers--Reset States D7 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh PCON* Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved SMR** Reserved SMR2* X X X X X X 0 0 0 0 1 0 0 0 0 0 1 D6 1 D5 1 D4 1 D3 1 D2 1 D1 1 D0 0
Note: *Not reset with a Stop-Mode Recovery. Note: **Not reset with a Stop-Mode Recovery except Bit D7.
PS022701-0104
Z87233 CMOS Z8" MCU Consumer Controller Processor
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Table 31. Expanded Register File Registers--Reset States (Continued) D7 0Eh 0Fh Reserved WDTMR* X X X 0 1 1 0 1 D6 D5 D4 D3 D2 D1 D0
Note: *Not reset with a Stop-Mode Recovery. Note: **Not reset with a Stop-Mode Recovery except Bit D7.
Port Configuration Register The Port Configuration Register, PCON, controls the configurations of Ports 0, 2, and 3. WRITE and reset states for bits D7-D0 are listed in Table 32.
Table 32. Port Configuration Register--PCON 00h/R0 Bank Fh: WRITE ONLY Bit R/W Reset
Note: W = Write.
D7 W 1
D6 W 1
D5 W 1
D4 W 1
D3 W 1
D2 W 1
D1 W 1
D0 W 0
Bit Position D7
Bit Field Oscillator
R/W W
Reset State Description 1 Low-EMI Oscillator 0: Low EMI 1: Standard Port 3 0: Low EMI 1: Standard Port 2 0: Low EMI 1: Standard Reserved 1: Reserved must be "1" Port 0 0: Low EMI 1: Standard Port 0 0: Open-Drain 1: Push-Pull Active
D6
Port 3 I/O
W
1
D5
Port 2 I/O
W
1
D4 D3
Reserved Port 0 I/O
W W
1 1
D2
Port 0 I/O
W
1
PS022701-0104
Z87233 CMOS Z8" MCU Consumer Controller Processor
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Bit Position D1 D0
Bit Field Reserved Port 3
R/W W W
Reset State Description 1 0 Reserved 1: Reserved must be "1" Port 3 Comparator Output 0: P34, P37 Standard Output 1: P34, P37 Comparator Output
Stop-Mode Recovery Register The Stop-Mode Recovery Register, SMR, controls clocking functions. READ/ WRITE and reset states for bits D7-D0 are listed in Table 33.
Table 33. Stop-Mode Recovery Register--SMR 0Bh/R11 Bank Fh:READ/WRITE Bit R/W Reset D7 R 0 D6 W 0 D5 W 1 D4 W 0 D3 W 0 D2 W 0 D1 W 0 D0 W 0
Note: R = Read, W = Write.
Bit Position D7
Bit Field Stop
R/W R
Reset State Description 0 Stop Flag3 0: POR 1: Stop Recovery Stop-Mode Recovery Level 0: Low 1: High Stop Delay 0: Off 1: On
D6
Stop-Mode Recovery Stop Delay
W
0
D5
W
1
Notes: 1. For the Stop-Mode Recovery Source, either SMR or SMR2 can be selected. If SMR is used to select the Stop-Mode Recovery Source, bits D1-D0 of SMR2 must be 0. 2. Cleared by RESET and SMR. 3. Not reset after Stop-Mode Recovery.
PS022701-0104
Z87233 CMOS Z8" MCU Consumer Controller Processor
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Bit Position D4-D2
Bit Field Stop Mode
R/W W
Reset State Description 000 Stop-Mode Recovery Source2 000: POR only and/or external RESET 001: P30 010: P31 011: P32 100: P33 101: P27 110: P2 NOR 0-3 111: P2 NOR 0-7 External Clock Divide-by-2 0: SCLK &TCLK = XIN / 2 1: SCLK &TCLK = X IN SCLK/TCLK Divide-by-16 0: Off 1: On
D1
Clock
W
0
D0
SCLK/TCLK
W
0
Notes: 1. For the Stop-Mode Recovery Source, either SMR or SMR2 can be selected. If SMR is used to select the Stop-Mode Recovery Source, bits D1-D0 of SMR2 must be 0. 2. Cleared by RESET and SMR. 3. Not reset after Stop-Mode Recovery.
Stop-Mode Recovery Register 2 The Stop-Mode Recovery Register, SMR2, controls additional Port 2 clocking functions. WRITE and reset states for bits D7-D0 are listed in Table 34.
Table 34. Stop-Mode Recovery Register 2--SMR2 0Dh/R13 Bank Fh: WRITE ONLY Bit R/W Reset D7 W X D6 W X D5 W X D4 W X D3 W X D2 W X D1 W 0 D0 W 0
Note: W = Write, X = Indeterminate.
Bit Position
Bit Field
R/W
Reset State Description
Note: For the Stop-Mode Recovery Source, either SMR or SMR2 can be selected. If SMR2 is used to select the Stop-Mode Recovery Source, bits D4-D2 of SMR must be 0. Not used in conjunction with SMR Source.
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Z87233 CMOS Z8" MCU Consumer Controller Processor
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D7-D2 D1-D0
Reserved STOP Mode
W W
X 00
Reserved--must be 0 Stop-Mode Recovery Source 2* 00: POR only 01: AND P20, P21, P22, P23 10: AND P20, P21, P22, P23, P24, P25, P26, P27 11: Reserved
Note: For the Stop-Mode Recovery Source, either SMR or SMR2 can be selected. If SMR2 is used to select the Stop-Mode Recovery Source, bits D4-D2 of SMR must be 0. Not used in conjunction with SMR Source.
Watch-Dog Timer Mode Register The Watch-Dog Timer Mode Register, WDTMR, controls Watch-Dog Timer functions. WRITE and reset states for bits D7-D0 are listed in Table 35.
Table 35. Watch-Dog Timer Mode Register--WDTMR 0Fh/R15 Bank Fh: WRITE ONLY Bit R/W Reset D7 W X D6 W X D5 W X D4 W 0 D3 W 1 D2 W 1 D1 W 0 D0 W 1
Note: W = Write, X = Indeterminate.
Bit Bit Position Field D7-D5 D4 Reserved XIN
R/W W W
Reset State Description X 0 Reserved--must be 0 X IN Input/Internal RC Select for WDT 0: On-Board RC 1: X IN WDT During STOP 0: WDT disabled during STOP mode 1: WDT enabled during STOP mode WDT During HALT 0: WDT disabled during HALT mode 1: WDT enabled during HALT mode WDT Tap Int. RC Osc. 00: 3.5 ms 01: 7 ms 10: 14 ms 11: 56 ms System Clock 128 SCLK 256 SCLK 512 SCLK 2048 SCLK
D3
WDT
W
1
D2
WDT
W
1
D1-D0
WDT Tap
W
01
Note: Not used in conjunction with SMR Source.
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Z87233 CMOS Z8" MCU Consumer Controller Processor
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Electrical Characteristics
Absolute Maximum Ratings
Stresses greater than the Absolute Maximum Ratings listed in Table 36 may cause permanent damage to the device. This rating is a stress rating only. Functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability.
Table 36. Absolute Maximum Ratings Parameter Ambient Temperature under Bias Storage Temperature Voltage on any Pin with Respect to VSS Voltage on VDD Pin with Respect to VSS Voltage on XIN Pin with Respect to VSS Total Power Dissipation Maximum Allowable Current out of VSS Maximum Allowable Current into VDD Maximum Allowable Current into an Input Pin Maximum Allowable Current into an Open-Drain Pin Maximum Allowable Output Current Sunk by Any I/O Pin Maximum Allowable Output Current Sourced by Any I/O Pin -600 -600 Min -40 -65 -0.6 -0.3 -0.6 Max +105 +150 +7 +7 VDD+1 1.21 220 180 +600 +600 25 25 Units C C V V V W mA mA A A mA mA 3 4 2 1 Notes
Notes: 1. Applies to all pins except Crystal pins and where otherwise noted. 2. There is no input protection diode from pin to VDD and current into pin is limited to 600 A. 3. Excludes XIN and XOUT pins. 4. Device pin is not at an output Low state.
Total power dissipation should not exceed 1.21 W for the package. Power dissipation is calculated as follows:
Total Power Dissipation = VDD x [IDD - (sum of IOH), + sum of [(VDD - VOH) x IOH] + sum of (VOL x IOL)
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Z87233 CMOS Z8" MCU Consumer Controller Processor
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DC Electrical Characteristics
Standard Temperature Range
Table 37. DC Electrical Characteristics at Standard Temperature TA = 0C to +70C Sym VCH Parameter VCC1 Min 0.7 VCC Max VCC+0.3
Typical2 @25C 1.8
Units Conditions V Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator
Notes
Clock Input 3.0V High Voltage 5.5V
0.7 VCC
VCC+0.3
2.6
V
VCL
Clock Input Low Voltage
3.0V
GND-0.3
0.2 VCC
1.2
V
5.5V
GND-0.3
0.2 VCC
2.1
V
VIH VIL VOH
Input High Voltage Input Low Voltage Output High Voltage
3.0V 5.5V 3.0V 5.5V 3.0V 5.0V
0.7 VCC 0.7 VCC GND-0.3 GND-0.3 VCC-0.4 VCC-0.4
VCC+0.3 VCC+0.3 0.2 VCC 0.2 VCC
1.8 2.6 1.1 1.6 3.1 4.8
V V V V V V IOH = -0.5 mA 4 IOH = -0.5 mA 4
Notes: 1. The VCC voltage specification of 3.0V guarantees 3.3V 0.3V with typicals at VCC = 3.3V, and the VCC voltage specification of 5.5V guarantees 5.0V 0.5V with typicals at VCC = 5.0V. 2. Typical voltage is VCC = 5.0V and 3.3V. 3. STANDARD Mode (not Low-EMI Mode). 4. Low-EMI Mode (Not Standard Mode). 5. For analog comparator, inputs when analog comparators are enabled. 6. All outputs unloaded, I/O pins floating, inputs at rail. 7. Same as note 6, except inputs at VCC. 8. Clock must be forced Low, when XIN is clock-driven and XOUT is floating. 9. 0C to 70C (standard temperature). 10. Autolatch (Mask Option) selected. 11. The VLV voltage increases as the temperature decreases and overlaps lower VCC operating region. See Figure 15. 12. -40C to 105C (extended temperature).
PS022701-0104
Z87233 CMOS Z8" MCU Consumer Controller Processor
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Table 37. DC Electrical Characteristics at Standard Temperature (Continued) TA = 0C to +70C Sym VOH1 VOL VOL1 VOL2 Parameter Output High Voltage Output Low Voltage Output Low Voltage Output Low Voltage VCC1 3.0V 5.5V 3.0V 5.0V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V -1 -1 -1 -1 Min VCC-0.4 VCC-0.4 0.6 0.4 0.6 0.4 1.2 1.2 25 25 2 2 1 1 10 15 Max
Typical2 @25C 3.1 4.8 0.2 0.1 0.2 0.1 0.3 0.4 10 10 0.04 0.04 0.04 0.04 4 9
Units Conditions V V V V V V V V mV mV A A A A mA mA VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC @ 4 MHz @ 4 MHz
Notes
IOH = -2.0 mA 3 IOH = -2.0 mA 3 IOL = 1.0 mA IOL = 1.0 mA 4 4
IOL = +4.0 mA 3 IOL = +4.0 mA 3 IOL = +6 mA IOL = +12 mA 3 3 5 5
VOFFSET Comparator Input Offset Voltage IIL IOL ICC Input Leakage Output Leakage Supply Current
6 6
Notes: 1. The VCC voltage specification of 3.0V guarantees 3.3V 0.3V with typicals at VCC = 3.3V, and the VCC voltage specification of 5.5V guarantees 5.0V 0.5V with typicals at VCC = 5.0V. 2. Typical voltage is VCC = 5.0V and 3.3V. 3. STANDARD Mode (not Low-EMI Mode). 4. Low-EMI Mode (Not Standard Mode). 5. For analog comparator, inputs when analog comparators are enabled. 6. All outputs unloaded, I/O pins floating, inputs at rail. 7. Same as note 6, except inputs at VCC. 8. Clock must be forced Low, when XIN is clock-driven and XOUT is floating. 9. 0C to 70C (standard temperature). 10. Autolatch (Mask Option) selected. 11. The VLV voltage increases as the temperature decreases and overlaps lower VCC operating region. See Figure 15. 12. -40C to 105C (extended temperature).
PS022701-0104
Z87233 CMOS Z8" MCU Consumer Controller Processor
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Table 37. DC Electrical Characteristics at Standard Temperature (Continued) TA = 0C to +70C Sym ICC1 Parameter VCC1 Min 4.3 7 8 10 500 800 0 0 VCC-1.0V VCC-1.0V Max
Typical2 @25C 1.5 3.4 2 4 310 600
Units Conditions mA mA A A A A V V
Notes
Standby 3.0V Current (HALT mode) 5.5V Standby Current (STOP Mode) 3.0V 5.5V 3.0V 5.5V
VIN = 0V, VCC 6 @ 4 MHz VIN = 0V, VCC 6 @ 4 MHz WDT is not Running WDT is not Running WDT is Running WDT is Running 7,8 7,8 7,8,9 7,8,9 5 5
ICC2
VICR
Input Common Mode Voltage Range Autolatch Low Current
3.0V 5.5V
IALL IALH
3.0V 5.5V
8 15 -5 -8
3 5 -3 -6
A A A A
0V10 10 10 10
Autolatch 3.0V High Current 5.5V
Notes: 1. The VCC voltage specification of 3.0V guarantees 3.3V 0.3V with typicals at VCC = 3.3V, and the VCC voltage specification of 5.5V guarantees 5.0V 0.5V with typicals at VCC = 5.0V. 2. Typical voltage is VCC = 5.0V and 3.3V. 3. STANDARD Mode (not Low-EMI Mode). 4. Low-EMI Mode (Not Standard Mode). 5. For analog comparator, inputs when analog comparators are enabled. 6. All outputs unloaded, I/O pins floating, inputs at rail. 7. Same as note 6, except inputs at VCC. 8. Clock must be forced Low, when XIN is clock-driven and XOUT is floating. 9. 0C to 70C (standard temperature). 10. Autolatch (Mask Option) selected. 11. The VLV voltage increases as the temperature decreases and overlaps lower VCC operating region. See Figure 15. 12. -40C to 105C (extended temperature).
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Z87233 CMOS Z8" MCU Consumer Controller Processor
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Table 37. DC Electrical Characteristics at Standard Temperature (Continued) TA = 0C to +70C Sym VLV Parameter VCC Low Voltage Protection Voltage VCC1 2.2 Min 3.1 Max
Typical2 @25C 2.8
Units Conditions V
Notes 11
Notes: 1. The VCC voltage specification of 3.0V guarantees 3.3V 0.3V with typicals at VCC = 3.3V, and the VCC voltage specification of 5.5V guarantees 5.0V 0.5V with typicals at VCC = 5.0V. 2. Typical voltage is VCC = 5.0V and 3.3V. 3. STANDARD Mode (not Low-EMI Mode). 4. Low-EMI Mode (Not Standard Mode). 5. For analog comparator, inputs when analog comparators are enabled. 6. All outputs unloaded, I/O pins floating, inputs at rail. 7. Same as note 6, except inputs at VCC. 8. Clock must be forced Low, when XIN is clock-driven and XOUT is floating. 9. 0C to 70C (standard temperature). 10. Autolatch (Mask Option) selected. 11. The VLV voltage increases as the temperature decreases and overlaps lower VCC operating region. See Figure 15. 12. -40C to 105C (extended temperature).
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Extended Temperature Range
Table 38. DC Electrical Characteristics at Extended Temperature TA = -40C to +105C Sym VCH Parameter Clock Input High Voltage VCC1 3.0V Min 0.7 VCC Max VCC+0.3 Typical2 @25C 1.8
Units V
Conditions Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator
Notes
5.5V
0.7 VCC
VCC+0.3
2.6
V
VCL
Clock Input Low Voltage
3.0V
GND-0.3
0.2 VCC
1.2
V
5.5V
GND-0.3
0.2 VCC
2.1
V
VIH VIL VOH VOH1
Input High Voltage Input Low Voltage Output High Voltage Output High Voltage
3.0V 5.5V 3.0V 5.5V 3.0V 5.0V 3.0V 5.5V
0.7 VCC 0.7 VCC GND-0.3 GND-0.3 VCC-0.4 VCC-0.4 VCC-0.4 VCC-0.4
VCC+0.3 VCC+0.3 0.2 VCC 0.2 VCC
1.8 2.6 1.1 1.6 3.1 4.8 3.1 4.8
V V V V V V V V IOH = -0.5 mA 4 IOH = -0.5 mA 4 IOH = -2.0 mA 3 IOH = -2.0 mA 3
Notes: 1. The VCC voltage specification of 3.0V guarantees 3.3V 0.3V with typicals at VCC = 3.3V, and the VCC voltage specification of 5.5V guarantees 5.0V 0.5V with typicals at VCC = 5.0V. 2. Typical voltage is VCC = 5.0V and 3.3V. 3. STANDARD Mode (not Low-EMI Mode). 4. Low-EMI Mode (Not Standard Mode). 5. For analog comparator, inputs when analog comparators are enabled. 6. All outputs unloaded, I/O pins floating, inputs at rail. 7. Same as note 6, except inputs at VCC. 8. Clock must be forced Low, when XIN is clock-driven and XOUT is floating. 9. 0C to 70C (standard temperature). 10. Autolatch (Mask Option) selected. 11. The VLV voltage increases as the temperature decreases and overlaps lower VCC operating region. See Figure 15. 12. -40C to 105C (extended temperature).
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Table 38. DC Electrical Characteristics at Extended Temperature (Continued) TA = -40C to +105C Sym VOL Parameter Output Low Voltage Output Low Voltage Output Low Voltage VCC1 3.0V 5.0V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V -1 -1 -1 -1 Min Max 0.6 0.4 0.6 0.4 1.2 1.2 25 25 2 2 2 2 10 15 4.3 7 Typical2 @25C 0.2 0.1 0.2 0.1 0.3 0.4 10 10 0.04 0.04 0.04 0.04 4 9 1.5 3.4
Units V V V V V V mV mV A A A A mA mA mA mA
Conditions IOL = 1.0 mA IOL = 1.0 mA
Notes 4 4
VOL1 VOL2
IOL = +4.0 mA 3 IOL = +4.0 mA 3 IOL = +6 mA IOL = +12 mA 3 3 5 5 VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC @ 4 MHz @ 4 MHz 6 6
VOFFSET Comparator Input Offset Voltage IIL IOL ICC ICC1
Input Leakage 3.0V 5.5V Output Leakage 3.0V 5.5V
Supply Current 3.0V 5.5V Standby Current (HALT mode) 3.0V 5.5V
VIN = 0V, VCC 6 @ 4 MHz VIN = 0V, VCC 6 @ 4 MHz
Notes: 1. The VCC voltage specification of 3.0V guarantees 3.3V 0.3V with typicals at VCC = 3.3V, and the VCC voltage specification of 5.5V guarantees 5.0V 0.5V with typicals at VCC = 5.0V. 2. Typical voltage is VCC = 5.0V and 3.3V. 3. STANDARD Mode (not Low-EMI Mode). 4. Low-EMI Mode (Not Standard Mode). 5. For analog comparator, inputs when analog comparators are enabled. 6. All outputs unloaded, I/O pins floating, inputs at rail. 7. Same as note 6, except inputs at VCC. 8. Clock must be forced Low, when XIN is clock-driven and XOUT is floating. 9. 0C to 70C (standard temperature). 10. Autolatch (Mask Option) selected. 11. The VLV voltage increases as the temperature decreases and overlaps lower VCC operating region. See Figure 15. 12. -40C to 105C (extended temperature).
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Table 38. DC Electrical Characteristics at Extended Temperature (Continued) TA = -40C to +105C Sym ICC2 Parameter VCC1 Min Max 8 10 600 1000 0 0 VCC-1.5V VCC-1.5V 10 20 -7 -10 2.0 3.3 3 5 -3 -6 2.8 Typical2 @25C 2 4 310 600
Units A A A A V V A A A A V
Conditions WDT is not Running WDT is not Running WDT is Running WDT is Running
Notes 7,8 7,8 7,8 7,8 5 5
Standby 3.0V Current (STOP Mode) 5.5V 3.0V 5.5V
VICR
Input Common 3.0V Mode Voltage 5.5V Range Autolatch Low Current 3.0V 5.5V
IALL IALH VLV
0V10 10 10 10 11,12
Autolatch High 3.0V Current 5.5V VCC Low Voltage Protection Voltage
Notes: 1. The VCC voltage specification of 3.0V guarantees 3.3V 0.3V with typicals at VCC = 3.3V, and the VCC voltage specification of 5.5V guarantees 5.0V 0.5V with typicals at VCC = 5.0V. 2. Typical voltage is VCC = 5.0V and 3.3V. 3. STANDARD Mode (not Low-EMI Mode). 4. Low-EMI Mode (Not Standard Mode). 5. For analog comparator, inputs when analog comparators are enabled. 6. All outputs unloaded, I/O pins floating, inputs at rail. 7. Same as note 6, except inputs at VCC. 8. Clock must be forced Low, when XIN is clock-driven and XOUT is floating. 9. 0C to 70C (standard temperature). 10. Autolatch (Mask Option) selected. 11. The VLV voltage increases as the temperature decreases and overlaps lower VCC operating region. See Figure 15. 12. -40C to 105C (extended temperature).
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AC Electrical Characteristics
The timing characteristics with respect to external input/output sources are provided in the following pages. Additional Timing Figure 16 illustrates the timing characteristics with respect to system clock functions. See Tables 39 and 40 for descriptions of the numbered timing parameters in the figure.
1 Clock
3
2 7 TN 7
2
3
4 6 IRQN
5
8
9
Clock Setup 11
12
Figure 16.Additional Timing
The values presented in Table 39 are within a standard temperature range of 0C to 70C.
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Table 39. Additional Timing at Standard Temperature TA = 0C to +70C 4 MHz No Sym 1 TPC TRC, TFC TWC TWTINL TWTINH TPTIN TRTIN, TFTIN TWIL TWIL Parameter Input Clock Period VCC1 3.0V 5.5V 2 Clock Input Rise & Fall 3.0V Times 5.5V Input Clock Width 3.0V 5.5V 4 Timer Input Low Width 3.0V 5.5V 5 Timer Input High Width 3.0V 5.5V 6 Timer Input Period 3.0V 5.5V 7 Timer Input Rise & Fall 3.0V Timer 5.5V Interrupt Request Low 3.0V Time 5.5V Interrupt Request Low 3.0V Time 5.5V 100 70 5TPC 5TPC 125 125 100 70 5TPC 5TPC 8TPC 8TPC 100 100 ns ns ns ns Min 250 250 Max DC DC 15 15 Units ns ns ns ns ns ns ns ns Notes 2,3,4 2,3,4 2,3 2,3 2,3,4 2,3,4 2,3 2,3 2,3 2,3 2,3 2,3 2,3 2,3 2,3,5 2,3,5 2,3,6 2,3,6 D1,D0
3
8A
8B
Notes: 1. The VCC voltage specification of 3.0V guarantees 3.3V 0.3V, and the VCC voltage specification of 5.5V guarantees 5.0V 0.5V. 2. Timing reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 3. SMR: D1 = 0. 4. The maximum frequency for the external crystal clock is 4 MHz when using LOW-EMI OSCILLATOR mode. 5. The interrupt request via Port 3 (P31-P33). 6. The interrupt request via Port 3 (P30). 7. SMR: D5 = 1, and the POR Stop-Mode Delay is on. 8. For RC and LC oscillators, and for an oscillator driven by a clock driver. 9. The D1,D0 column applies to the Watch-Dog Timer Mode Register tap selection. 10. 12 s is the typical delay time; only applies when SMR Register bit D5 is cleared to 0
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Table 39. Additional Timing at Standard Temperature (Continued) TA = 0C to +70C 4 MHz No Sym 9 TWIH TWSM TOST TWDT Parameter VCC1 Min 5TPC 5TPC 12 12 5TPC 5TPC 7 3.5 14 7 28 14 112 56 3 1.5 24 13 ms ms ms ms ms ms ms ms ms ms ns ns Max Units Notes 2,3,5 2,3,5 7 7 7,8 7,8 9 9 9 9 9 9 9 9 0,0 0,0 0,1 0,1 1,0 1,0 1,1 1,1 D1,D0
Interrupt Request Input 3.0V High Time 5.5V Stop-Mode Recovery Width Spec 3.0V 5.5V
10
11
Oscillator Startup Time 3.0V 5.5V
12
Watch-Dog Timer Delay Timer before time-out
3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V
13
TPOR
Power-On Reset Delay 3.0V 5.5V
Notes: 1. The VCC voltage specification of 3.0V guarantees 3.3V 0.3V, and the VCC voltage specification of 5.5V guarantees 5.0V 0.5V. 2. Timing reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 3. SMR: D1 = 0. 4. The maximum frequency for the external crystal clock is 4 MHz when using LOW-EMI OSCILLATOR mode. 5. The interrupt request via Port 3 (P31-P33). 6. The interrupt request via Port 3 (P30). 7. SMR: D5 = 1, and the POR Stop-Mode Delay is on. 8. For RC and LC oscillators, and for an oscillator driven by a clock driver. 9. The D1,D0 column applies to the Watch-Dog Timer Mode Register tap selection. 10. 12 s is the typical delay time; only applies when SMR Register bit D5 is cleared to 0
The values presented in Table 40 are within the extended temperature range of - 40C to 105C.
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Table 40. Additional Timing at Extended Temperature TA = -40C to +105C 4 MHz No Sym 1 TPC TRC, TFC TWC TWTINL TWTINH TPTIN TRTIN, TFTIN TWIL TWIL Parameter Input Clock Period VCC1 Min 3.0V 250 5.5V 250 2 Clock Input Rise & Fall 3.0V Times 5.5V Input Clock Width 3.0V 125 5.5V 125 4 Timer Input Low Width 3.0V 100 5.5V 70 5 Timer Input High Width 3.0V 5TPC 5.5V 5TPC 6 Timer Input Period 3.0V 8TPC 5.5V 8TPC 7 Timer Input Rise & Fall 3.0V Timer 5.5V Interrupt Request Low 3.0V 100 Time 5.5V 70 Interrupt Request Low 3.0V 5TPC Time 5.5V 5TPC 100 100 ns ns ns ns Max DC DC 15 15 Units ns ns ns ns ns ns ns ns Notes D1,D0 2,3,4 2,3,4 2,3 2,3 2,3,4 2,3,4 2,3 2,3 2,3 2,3 2,3 2,3 2,3 2,3 2,3,5 2,3,5 2,3,6 2,3,6
3
8A
8B
Notes: 1. The VCC voltage specification of 5.5V guarantees 5.0V 0.5V. 2. The timing reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 3. SMR: D1 = 0. 4. The maximum frequency for the external crystal clock is 4 MHz when using LOW-EMI OSCILLATOR mode. 5. The interrupt request via Port 3 (P31-P33). 6. The interrupt request via Port 3 (P30). 7. SMR: D5 = 1, and the POR Stop-Mode Delay is on. 8. For RC and LC oscillators, and for an oscillator driven by a clock driver. 9. The D1,D0 column applies to the Watch-Dog Timer Mode Register tap selection. 10. 12 s is the typical delay time.
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Table 40. Additional Timing at Extended Temperature (Continued) TA = -40C to +105C 4 MHz No Sym 9 TWIH TWSM TOST TWDT Parameter VCC1 Min Max Units Notes D1,D0 2,3,5 2,3,5 ns ns 5TPC 5TPC ms ms ms ms ms ms ms ms 25 14 ms ms 7 7 7,8 7,8 9 9 9 9 9 9 9 9 0,0 0,0 0,1 0,1 1,0 1,0 1,1 1,1
Interrupt Request Input 3.0V 5TPC High Time 5.5V 5TPC Stop-Mode Recovery Width Spec 3.0V 5.5V 12 12
10
11
Oscillator Startup Time 3.0V 5.5V
12
Watch-Dog Timer Delay Timer before time-out
3.0V 7 5.5V 3.5 3.0V 14 5.5V 7 3.0V 28 5.5V 14 3.0V 112 5.5V 56
13
TPOR
Power-On Reset Delay 3.0V 3 5.5V 1
Notes: 1. The VCC voltage specification of 5.5V guarantees 5.0V 0.5V. 2. The timing reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 3. SMR: D1 = 0. 4. The maximum frequency for the external crystal clock is 4 MHz when using LOW-EMI OSCILLATOR mode. 5. The interrupt request via Port 3 (P31-P33). 6. The interrupt request via Port 3 (P30). 7. SMR: D5 = 1, and the POR Stop-Mode Delay is on. 8. For RC and LC oscillators, and for an oscillator driven by a clock driver. 9. The D1,D0 column applies to the Watch-Dog Timer Mode Register tap selection. 10. 12 s is the typical delay time.
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Standard Test Conditions
The characteristics listed in following pages apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (see Figure 17.)
From Output Under Test
150 pF
Figure 17.Test Load Diagram
Capacitance
Table 41. Capacitance* Parameter Input capacitance Output capacitance I/O capacitance Min 0 0 0 Max 12 pF 12 pF 12 pF
Note: *TA = 25C, VCC = GND = 0V, f = 1.0 MHz, unmeasured pins to GND.
Packaging
Figure 18 illustrates the 28-pin DIP package.
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Figure 18.28-Pin DIP Package Diagram
Figure 19 illustrates the 28-pin SOIC package.
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Figure 19.28-Pin SOIC Package Diagram
Ordering Information
Table 42. Ordering Information Temperature Standard Standard Extended Speed (4MHz) 4 4 4 Pin Count 28 28 28 Package DIP SOIC DIP Order Number* Z8723304PSC Z8723304SSC Z8723304PEC
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Table 42. Ordering Information Temperature Extended Speed (4MHz) 4 Pin Count 28 Package SOIC Order Number* Z8723304SEC
Note: *The Standard temperature range is 0C to 70C. For parts that operate in the Extended temperature range of -40C to 105C, substitute the letter E for the letter S. For example, the Order Number for a 28-pin DIP operating in the Extended temperature range is Z8723304PEC.
For fast results, contact your local ZiLOG sale office for assistance in ordering the part(s) desired.
Precharacterization Product
The product represented by this document is newly introduced and ZiLOG has not completed the full characterization of the product. The document states what ZiLOG knows about this product at this time, but additional features or non-conformance with some aspects of the document may be found, either by ZiLOG or its customers in the course of further application and characterization work. In addition, ZiLOG cautions that delivery may be uncertain at times, due to start-up yield issues. ZiLOG, Inc. 532 Race Street San Jose, CA 95126-3432 Telephone (408) 558-8500 FAX 408 558-8300 Internet: www.ZiLOG.com
Document Information
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PS022701-0104
Z87233 CMOS Z8" MCU Consumer Controller Processor
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01 0104
Revision Number Month and Year Published
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Z87233 Product Specification
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